1. Field of the Invention
The present invention relates to an apparatus for controlling a word line decoder, more particularly to an apparatus that turns on the word line decoder by monitoring the reference bit line equalization.
2. Description of the Prior Art
In static random access memory (SRAM), each SRAM cell couples to a bit line (BL) and a bit line bar (BL′). Before the cell performs read or write cycle, the BL and the associated BL′ of the SRAM cell must be equalized, i.e., the voltages of BL and the BL′ must be pulled to same voltage level and this voltage level must be above flip voltage of the SRAM cell. Thus, writing error data to the cell due to wrong timing can be avoided.
FIG. 1 is a block diagram of a conventional asynchronous SRAM circuit. The SRAM cell array is divided into many sections to speed up the cell access speed. Here a section of cell array is illustrated. ABUF 100 is an address buffer for latching an external address XA to generate an address A internally used in a chip. address A includes two major parts; one is named word line address, the other is named bit line address. Main word line (MWL) decoder 102 and Sub-WL pre-decoder 104 receives word line address to generate MWL, sw0, and sw1 after decoding. One of the sw0 and sw1, and MWL will be decoded at sub-WL decoder 118 to excite a selected word line of a selected section. Column decoder 106 includes a section selector and a bit line address decoder to generate section enable signal (SEC) and bit switch (BS) enable signal (LBL). SEC and LBL can enable BS to select a bit line pair (BL pair). SEC is also sent to the sub-WL pre-decoder 104 to enable the pre-decoder, as shown in FIG. 2. Address transition detection (ATD) circuit generates ATD signal when the address is toggled. ATD signal will trigger bit line (BL) equalization initiation circuit to activate BPCB signal, which turns on bit line equalization circuit 112. BL equalization is performed during the active duration of BPCB signal.
From above, it is clear that there must be a close timing relationship between the toggling of WL and equalization of BL. If WL turns on before the completion of BL equalization, wrong data will be written into the selected cell and thus produces error in data access. Therefore, this timing relationship must be avoided by circuit design. Synchronous SRAM also has the same design consideration.
In SRAM design, timing for turning on a selected word line is controlled, so that the timing for any word line to be turned on must be after the equalization of the bit lines. Thus, SRAM designer must find out the specific word lines that are turned on most quickly during decoding operation, and adequately adjust the timing of row decoder (main word line decoder 102 and sub-WL pre-decoder 104) to satisfy the above design requirement. But the above method not only delays the timing to turn on the fastest WL, but also the timing of the slowest WL. This increases the access time of the memory chip and causes speed loss. Furthermore, when designer does not find out the timing of the fastest WL correctly, the timing requirement may be violated. Process variation is another cause to violate this requirement.
U.S. Pat. No. 5,268,863 mentioned a method of assuring equalization of BL before WL turns on, but this patent is only suitable when the operation is switched from writing to reading. In U.S. Pat. No. 5,268,863 patent, the control signal WED corresponded to a write enable signal serves to control the turn-on of WL, thereby preventing problems that occur when address changes earlier than write enable. However, U.S. Pat. No. 5,268,863 does not handle the problem of timing from BL equalization to WL turn-on.
U.S. Pat. No. 5,343,432 uses a signal generated when WL turns on, and feeds this signal back to ATD to disable the pulses generated by ATD. Thus, the equalization time of BL can be shortened; hence the data access time can be shortened. However, this method still does not solve the problem of WL turning on before BL equalization.